`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   04:33:51 04/03/2011
// Design Name:   FIRfilter
// Module Name:   C:/peter/enee408/project/FIRfilter/FIR_tb.v
// Project Name:  FIRfilter
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: FIRfilter
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module FIR_tb;

	parameter N=8,M=8,K=4;

	// Inputs
	reg [N-1:0] x_in;
	reg clock;
	reg setTaps;
	reg [(M*K)-1:0] taps;

	// Outputs
	wire [N+M-1:0] y_out;

	// Instantiate the Unit Under Test (UUT)
	FIRfilter #(.N(N),.M(M),.K(K)) uut (
		.x_in(x_in), 
		.y_out(y_out), 
		.clock(clock), 
		.setTaps(setTaps), 
		.taps(taps)
	);

	initial begin
	$monitor($time,, "a_in = %d,      s_out=%d"	, x_in, y_out);
		// Initialize Inputs
		x_in = 0;
		clock = 1;
		setTaps = 0;
		taps = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		
		//start by loading taps
		setTaps = 1;
		taps = {8'd1,8'd1,8'd1,8'd1};
		#5;
		
		setTaps=0;
		x_in=1;
		#5;
		
		x_in=2;
		#5;
		
		x_in=3;
		#5;
		
		x_in=4;
		#5;
		
		x_in=5;
		#5;

	end
   
	always begin
		#2.5 clock <= ~clock;
	end
	
endmodule

